1. Technical Field of the Invention
This invention pertains to chip carrier topology design, including wire bond finger placement. More particularly, it relates to a simulation technique for automating wire bond finger placement.
2. Background Art
Pin ball grid array (PBGA) substrates (also referred to as chip carriers) are used in the art for attachment of electronic chips. A chip is attached in the center of the substrate, and physical wiring connections made between the chip and the substrate via discrete wires. Chips have an array of bond pads around the perimeter to which these discrete wires are attached. An analogous bond bad on the substrate is the wire bond finger, referred to as fingers because they are usually long and narrow and fan out like the fingers of an outstretched hand. Thus, wire bond fingers are a series of I/O pads physically resident on a chip carrier and which connect to I/O pads on a chip. When the chip is placed within the cavity of a chip carrier, wires run out radially from the chip and are attached to the wire bond pads.
The creation of the wire bond fingers is usually one of the last steps in the process of attaching a chip to a substrate. This is because (1) a substrate is custom designed for the chip which will attach to it, and design of the substrate must wait until the chip design is complete; and (2) due to the ever increasing wiring density, uniqueness of each design and other factors at all levels of design of electronic components, it isn't feasible to create a standard set of wire bond fingers. The pads have to have a minimum size and spacing in order to accommodate automated wire bonding machines which physically attach wires during the manufacturing process. There is a minimum spacing requirement for the distance from the fingers to the encompassing chip carrier circuitry. Similarly, there is a minimum and maximum wire length for the wire which attaches the chip I/O to the wire bond finger. The fingers also must angle appropriately such that they lay along the axis of a straight line connecting the finger and the chip I/O to which it will connect. If the chip I/O is a voltage net (as distinguished from a signal net), then the wire connection will terminate at a voltage ring. Voltage rings are optional and when present encircle the chip and lie between the chip and the wire bond fingers.
While this recitation of the requirements and constraints for placement of wire bond fingers is illustrative and not exhaustive, it does convey the understanding that numerous criteria go into the placement of wire bond fingers, and that numerous parameters must be met in order for a wire bond finger pattern to qualify as a possible solution. A minor alteration to any one of the many parameters can lead to a different possible solution. Given the number of parameters and possible combinations, there can exist an almost limitless number of possible finger solutions. There is a need in the art to provide to the designer of electronic packages an understanding of possible solutions so that the best solution can be selected. The best solution is one which balances constraints such that all parameters are well within tolerance and the best possible use is made of the available substrate real estate.
As a result, a unique set of wire bond fingers is generated for each substrate/chip package. The wire bond fingers must be small enough to squeeze into the space available but large enough to meet packaging ground rules. The fingers must be placed at the appropriate angle (i.e., fan out or fan in) in order to support the printed wiring which will be attached on the substrate surface. The fingers must be spaced far enough apart to allow the wire bonder head to move past a finger without dislodging a discrete wire from on an adjacent finger. And each finger must meet minimum and maximum spacing guidelines from the chip as well as the surrounding substrate wiring.
Referring to FIG. 5, the constant bond length (CBL) finger style of the prior art is illustrated. FIG. 6 illustrates a zoom-in of the upper left corner of the design. As package circuit density has continued to increase, the CBL finger style has produced finger patterns which are less than optimal, often failing to take advantage of available real estate, especially in the corners.
The current art supports specification of chippad locations by identifying:
1. Location of first chippad. PA0 2. Location of last chippad. PA0 3. Total quantity of chippads per side (i.e., north, south, east, and west). PA0 1. The chippad locations for each side become non-symmetrical. No longer can the chippad layout for a single side be stepped and repeated about the origin. Now chippad locations have to be entered individually for each side. PA0 2. The chippad locations are no longer uniformly spaced. As a result, the only way to know the location of the chippads is for the user to specify the exact location of each pad. PA0 1. This is a manual activity which could be more efficiently and accurately performed by finger generation software. PA0 2. This incorrect wiring contributes to wasted real estate, since the minimum spacings at the voltage rings are generally smaller than the minimum spacing at the fingers.
Using this information, the location of chippads for a single side is generated. Then the data for a single side is stepped and repeated about the origin to generate chippad locations for all four sides. This technique works fine until the following problems arise:
Voltage rings are an optional component of a substrate carrier. When present, these rings encircle the chip and are used to wire a chippad to a specific voltage.
The current art for wire bond finger generation does not take voltage ring information into account. Rather, chip I/O pads are incorrectly routed to a wire bond finger. The designer then must manually correct the design data to terminate the bond line at the voltage ring. There are two problems with this approach:
It is an object of the invention to provide an improved system and method for the placement of fingers on a substrate carrier.
It is a further object of the invention to provide finger layout styles which achieve optimal finger layout, particularly in the corners.
It is a further object of the invention to provide a system and method for accommodating the layout of chippads on non-symmetrical sides.
It is a further object of the invention to provide a system and method for accommodating the layout of chippads which are not uniformly spaced.
It is a further object of the invention to provide a system and method for automatically wiring chip I/O pads to voltage rings.
It is a further object of the invention to increase designer productivity and to use new finger layout patterns which most effectively make use of available real estate for interconnect wiring between chip and chip carrier.
It is a further object of the invention to provide a system and method which advances the state of the art with regard to generation of wire bond finger data for chip carriers by improving designer productivity by automating activities previously done manually; improving manufacturability and reliability of the resultant product through the use of new finger layout styles; and optimize the use of available real estate via implementation of the new finger layout styles and the automatic wiring of chip I/O pads to voltage rings.